feat: cpu, memory, computer hdl

project-5-computer-architecture/hdl/CPU.hdl

@@ -71,7 +71,12 @@ CHIP CPU {
     And(a=isCInstruction, b=d1, out=loadAFromALU);
     Mux16(a=instruction, b=aluOut, sel=loadAFromALU,out=aRegIn);
     Or(a=isAInstruction, b=loadAFromALU, out=loadA);
-    Register(in=aRegIn, load=loadA, out=aRegOut);
+    Register(in=aRegIn, 
+            load=loadA, 
+            // Out
+            out=aRegOut, 
+            out[0..14]=addressM
+    );
 
     // D Register
     And(a=isCInstruction, b=d2, out=loadD);
@@ -84,12 +89,44 @@ CHIP CPU {
     ALU(x=dRegOut,
         y=aluYin,
         zx=c1, nx=c2, zy=c3, ny=c4 , f=c5 , no=c6 , 
-        out=aluOut , 
-        zr=aluZrOut , 
-        ng=aluNgOut 
+        zr=aluZrOut, 
+        ng=aluNgOut,
+        // Out
+        out=aluOut, 
+        out=outM
     );
-    
+
+    // IN in[16], reset, load, inc;
+    // OUT out[16];
+    // inc almost all the time. 
+    // only when not load. load = jump
+
+    // JGT
+    // not negative and not zero
+    Not(in=aluNgOut, out=notAluNgOut);
+    Not(in=aluZrOut, out=notAluZrOut);
+    And(a=notAluZrOut, b=notAluNgOut , out=isPositive);
+    And(a=isPositive, b=j3, out=shouldJumpJGT);
+    // JEQ
+    // Jump if zero can be checked it zr
+    And(a=aluZrOut, b=j2 , out=shouldJumpJEQ);
+    // JLT
+    // Jump if less than 0
+    And(a=aluNgOut, b=j1, out=shouldJumpJLT);
+
+    // Should Jump
+    Or(a=shouldJumpJGT, b=shouldJumpJEQ , out=shouldJumpJGTJEQ);
+    Or(a=shouldJumpJGTJEQ , b= shouldJumpJLT, out=hasJumpInstruction );
+
+    // And C instruction
+    And(a=hasJumpInstruction, b=isCInstruction , out=shouldJump);
+
+    //Inc
+    Not(in=shouldJump, out=shouldIncrement);
 
 
+    PC(in=aRegOut, load=shouldJump, inc=shouldIncrement, reset=reset , out[0..14]=pc);
 
+    // Out
+    And(a=isCInstruction, b=d3 , out=writeM);
 }