diff --git a/.DS_Store b/.DS_Store
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diff --git a/project-3-sequential-logic/.DS_Store b/project-3-sequential-logic/.DS_Store
new file mode 100644
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diff --git a/project-3-sequential-logic/hdl/Bit.hdl b/project-3-sequential-logic/hdl/Bit.hdl
new file mode 100755
index 0000000..a4cced3
--- /dev/null
+++ b/project-3-sequential-logic/hdl/Bit.hdl
@@ -0,0 +1,20 @@
+// This file is part of www.nand2tetris.org
+// and the book "The Elements of Computing Systems"
+// by Nisan and Schocken, MIT Press.
+// File name: projects/3/a/Bit.hdl
+/**
+ * 1-bit register:
+ * If load is asserted, the register's value is set to in;
+ * Otherwise, the register maintains its current value:
+ * if (load(t)) out(t+1) = in(t), else out(t+1) = out(t)
+ */
+
+ 
+CHIP Bit {
+    IN in, load;
+    OUT out;
+
+    PARTS:
+    Mux(a=dffOut, b= in, sel=load, out=muxOut);
+    DFF(in=muxOut,out=dffOut, out=out);
+}
\ No newline at end of file
diff --git a/project-3-sequential-logic/hdl/PC.hdl b/project-3-sequential-logic/hdl/PC.hdl
new file mode 100755
index 0000000..67e35ca
--- /dev/null
+++ b/project-3-sequential-logic/hdl/PC.hdl
@@ -0,0 +1,39 @@
+// This file is part of www.nand2tetris.org
+// and the book "The Elements of Computing Systems"
+// by Nisan and Schocken, MIT Press.
+// File name: projects/3/a/PC.hdl
+/**
+ * A 16-bit counter.
+ * if      reset(t): out(t+1) = 0
+ * else if load(t):  out(t+1) = in(t)
+ * else if inc(t):   out(t+1) = out(t) + 1
+ * else              out(t+1) = out(t)
+ */
+
+ /*
+ * Personal Notes
+ * 
+ * 
+ */
+CHIP PC {
+    
+    IN in[16], reset, load, inc;
+    OUT out[16];
+    
+    PARTS:
+
+    // Inc
+    Inc16(in=regOut, out=inc16Out);
+    Mux16(a=regOut, b=inc16Out, sel=inc, out=incOut);
+
+    // Load
+    Mux16(a=incOut, b=in, sel=load, out=loadOut);
+    
+    // Reset
+    Mux16(a=loadOut, b[0..15]=false, sel=reset, out=resetOut);
+    
+    
+    Register(in=resetOut, load=true , out=regOut, out=out);
+
+
+}
\ No newline at end of file
diff --git a/project-3-sequential-logic/hdl/RAM16K.hdl b/project-3-sequential-logic/hdl/RAM16K.hdl
new file mode 100755
index 0000000..e3c522f
--- /dev/null
+++ b/project-3-sequential-logic/hdl/RAM16K.hdl
@@ -0,0 +1,42 @@
+// This file is part of www.nand2tetris.org
+// and the book "The Elements of Computing Systems"
+// by Nisan and Schocken, MIT Press.
+// File name: projects/3/b/RAM16K.hdl
+/**
+ * Memory of 16K 16-bit registers.
+ * If load is asserted, the value of the register selected by
+ * address is set to in; Otherwise, the value does not change.
+ * The value of the selected register is emitted by out.
+ */
+CHIP RAM16K {
+    IN in[16], load, address[14];
+    OUT out[16];
+
+    PARTS:
+
+    // Figuring out which RAM4k to write to
+    DMux4Way(
+        in=load,
+        sel=address[12..13],
+        a=load01,
+        b=load02,
+        c=load03,
+        d=load04
+    );
+
+    // Writing the correct RAM address inside the register
+    RAM4K(in=in, load=load01, address=address[0..11],out=ram4Kout01);
+    RAM4K(in=in, load=load02, address=address[0..11],out=ram4Kout02);
+    RAM4K(in=in, load=load03, address=address[0..11],out=ram4Kout03);
+    RAM4K(in=in, load=load04, address=address[0..11],out=ram4Kout04);
+    
+    // Reading the selected RAM Register
+    Mux4Way16(
+        a=ram4Kout01,
+        b=ram4Kout02,
+        c=ram4Kout03,
+        d=ram4Kout04,
+        sel=address[12..13],
+        out=out
+    );
+}
\ No newline at end of file
diff --git a/project-3-sequential-logic/hdl/RAM4K.hdl b/project-3-sequential-logic/hdl/RAM4K.hdl
new file mode 100755
index 0000000..0cc6fbf
--- /dev/null
+++ b/project-3-sequential-logic/hdl/RAM4K.hdl
@@ -0,0 +1,55 @@
+// This file is part of www.nand2tetris.org
+// and the book "The Elements of Computing Systems"
+// by Nisan and Schocken, MIT Press.
+// File name: projects/3/b/RAM4K.hdl
+/**
+ * Memory of 4K 16-bit registers.
+ * If load is asserted, the value of the register selected by
+ * address is set to in; Otherwise, the value does not change.
+ * The value of the selected register is emitted by out.
+ */
+CHIP RAM4K {
+    IN in[16], load, address[12];
+    OUT out[16];
+
+    PARTS:
+    
+    // Figuring out which RAM512 to write to
+    DMux8Way(
+        in=load,
+        sel=address[9..11],
+        a=load01,
+        b=load02,
+        c=load03,
+        d=load04,
+        e=load05,
+        f=load06,
+        g=load07,
+        h=load08
+    );
+
+    // Writing the correct RAM address inside the register
+    RAM512(in=in, load=load01, address=address[0..8],out=ram512out01);
+    RAM512(in=in, load=load02, address=address[0..8],out=ram512out02);
+    RAM512(in=in, load=load03, address=address[0..8],out=ram512out03);
+    RAM512(in=in, load=load04, address=address[0..8],out=ram512out04);
+    
+    RAM512(in=in, load=load05, address=address[0..8],out=ram512out05);
+    RAM512(in=in, load=load06, address=address[0..8],out=ram512out06);
+    RAM512(in=in, load=load07, address=address[0..8],out=ram512out07);
+    RAM512(in=in, load=load08, address=address[0..8],out=ram512out08);
+
+    // Reading the selected RAM Register
+    Mux8Way16(
+        a=ram512out01,
+        b=ram512out02,
+        c=ram512out03,
+        d=ram512out04,
+        e=ram512out05,
+        f=ram512out06,
+        g=ram512out07,
+        h=ram512out08,
+        sel=address[9..11],
+        out=out
+    );
+}
\ No newline at end of file
diff --git a/project-3-sequential-logic/hdl/RAM512.hdl b/project-3-sequential-logic/hdl/RAM512.hdl
new file mode 100755
index 0000000..587c2c9
--- /dev/null
+++ b/project-3-sequential-logic/hdl/RAM512.hdl
@@ -0,0 +1,55 @@
+// This file is part of www.nand2tetris.org
+// and the book "The Elements of Computing Systems"
+// by Nisan and Schocken, MIT Press.
+// File name: projects/3/b/RAM512.hdl
+/**
+ * Memory of 512 16-bit registers.
+ * If load is asserted, the value of the register selected by
+ * address is set to in; Otherwise, the value does not change.
+ * The value of the selected register is emitted by out.
+ */
+CHIP RAM512 {
+    IN in[16], load, address[9];
+    OUT out[16];
+
+    PARTS:
+
+    // Figuring out which RAM64 to write to
+    DMux8Way(
+        in=load,
+        sel=address[6..8],
+        a=load01,
+        b=load02,
+        c=load03,
+        d=load04,
+        e=load05,
+        f=load06,
+        g=load07,
+        h=load08
+    );
+
+    // Writing the correct RAM address inside the register
+    RAM64(in=in, load=load01, address=address[0..5],out=ram64out01);
+    RAM64(in=in, load=load02, address=address[0..5],out=ram64out02);
+    RAM64(in=in, load=load03, address=address[0..5],out=ram64out03);
+    RAM64(in=in, load=load04, address=address[0..5],out=ram64out04);
+    
+    RAM64(in=in, load=load05, address=address[0..5],out=ram64out05);
+    RAM64(in=in, load=load06, address=address[0..5],out=ram64out06);
+    RAM64(in=in, load=load07, address=address[0..5],out=ram64out07);
+    RAM64(in=in, load=load08, address=address[0..5],out=ram64out08);
+
+    // Reading the selected RAM Register
+    Mux8Way16(
+        a=ram64out01,
+        b=ram64out02,
+        c=ram64out03,
+        d=ram64out04,
+        e=ram64out05,
+        f=ram64out06,
+        g=ram64out07,
+        h=ram64out08,
+        sel=address[6..8],
+        out=out
+    );
+}
\ No newline at end of file
diff --git a/project-3-sequential-logic/hdl/RAM64.hdl b/project-3-sequential-logic/hdl/RAM64.hdl
new file mode 100755
index 0000000..9d38e2f
--- /dev/null
+++ b/project-3-sequential-logic/hdl/RAM64.hdl
@@ -0,0 +1,55 @@
+// This file is part of www.nand2tetris.org
+// and the book "The Elements of Computing Systems"
+// by Nisan and Schocken, MIT Press.
+// File name: projects/3/a/RAM64.hdl
+/**
+ * Memory of sixty four 16-bit registers.
+ * If load is asserted, the value of the register selected by
+ * address is set to in; Otherwise, the value does not change.
+ * The value of the selected register is emitted by out.
+ */
+CHIP RAM64 {
+    IN in[16], load, address[6];
+    OUT out[16];
+
+    PARTS:
+
+    // Figuring out which RAM8 to write to
+    DMux8Way(
+        in=load,
+        sel=address[3..5],
+        a=load01,
+        b=load02,
+        c=load03,
+        d=load04,
+        e=load05,
+        f=load06,
+        g=load07,
+        h=load08
+    );
+
+    // Writing the correct RAM address inside the register
+    RAM8(in=in, load=load01, address=address[0..2],out=ram8out01 );
+    RAM8(in=in, load=load02, address=address[0..2],out=ram8out02 );
+    RAM8(in=in, load=load03, address=address[0..2],out=ram8out03 );
+    RAM8(in=in, load=load04, address=address[0..2],out=ram8out04 );
+    
+    RAM8(in=in, load=load05, address=address[0..2],out=ram8out05 );
+    RAM8(in=in, load=load06, address=address[0..2],out=ram8out06 );
+    RAM8(in=in, load=load07, address=address[0..2],out=ram8out07 );
+    RAM8(in=in, load=load08, address=address[0..2],out=ram8out08 );
+
+    // Reading the selected RAM Register
+    Mux8Way16(
+        a=ram8out01,
+        b=ram8out02,
+        c=ram8out03,
+        d=ram8out04,
+        e=ram8out05,
+        f=ram8out06,
+        g=ram8out07,
+        h=ram8out08,
+        sel=address[3..5],
+        out=out
+    );
+}
\ No newline at end of file
diff --git a/project-3-sequential-logic/hdl/RAM8.hdl b/project-3-sequential-logic/hdl/RAM8.hdl
new file mode 100755
index 0000000..7727c3c
--- /dev/null
+++ b/project-3-sequential-logic/hdl/RAM8.hdl
@@ -0,0 +1,55 @@
+// This file is part of www.nand2tetris.org
+// and the book "The Elements of Computing Systems"
+// by Nisan and Schocken, MIT Press.
+// File name: projects/3/a/RAM8.hdl
+/**
+ * Memory of eight 16-bit registers.
+ * If load is asserted, the value of the register selected by
+ * address is set to in; Otherwise, the value does not change.
+ * The value of the selected register is emitted by out.
+ */
+CHIP RAM8 {
+    IN in[16], load, address[3];
+    OUT out[16];
+
+    PARTS:
+
+    // Only writing if load = 1
+
+    // Selecting which address 16-bit register to write to 
+    DMux8Way(
+        sel=address,
+        in=load,
+        a=load1,
+        b=load2, 
+        c=load3, 
+        d=load4, 
+        e=load5, 
+        f=load6, 
+        g=load7, 
+        h=load8, 
+    );
+    // Writing to the selected register
+    Register(in=in , load=load1 , out= regOut1);
+    Register(in=in , load=load2 , out= regOut2);
+    Register(in=in , load=load3 , out= regOut3);
+    Register(in=in , load=load4 , out= regOut4);
+    Register(in=in , load=load5 , out= regOut5);
+    Register(in=in , load=load6 , out= regOut6);
+    Register(in=in , load=load7 , out= regOut7);
+    Register(in=in , load=load8 , out= regOut8);
+
+    // Outputting the register that is selected
+    Mux8Way16(
+        a=regOut1,
+        b=regOut2,
+        c=regOut3,
+        d=regOut4,
+        e=regOut5,
+        f=regOut6,
+        g=regOut7,
+        h=regOut8,
+        sel=address,
+        out=out
+    );
+}
\ No newline at end of file
diff --git a/project-3-sequential-logic/hdl/Register.hdl b/project-3-sequential-logic/hdl/Register.hdl
new file mode 100755
index 0000000..4c4a178
--- /dev/null
+++ b/project-3-sequential-logic/hdl/Register.hdl
@@ -0,0 +1,33 @@
+// This file is part of www.nand2tetris.org
+// and the book "The Elements of Computing Systems"
+// by Nisan and Schocken, MIT Press.
+// File name: projects/3/a/Register.hdl
+/**
+ * 16-bit register:
+ * If load is asserted, the register's value is set to in;
+ * Otherwise, the register maintains its current value:
+ * if (load(t)) out(t+1) = int(t), else out(t+1) = out(t)
+ */
+CHIP Register {
+    IN in[16], load;
+    OUT out[16];
+
+    PARTS:
+
+    Bit(in=in[0], load=load , out=out[0]);
+    Bit(in=in[1], load=load , out=out[1]);
+    Bit(in=in[2], load=load , out=out[2]);
+    Bit(in=in[3], load=load , out=out[3]);
+    Bit(in=in[4], load=load , out=out[4]);
+    Bit(in=in[5], load=load , out=out[5]);
+    Bit(in=in[6], load=load , out=out[6]);
+    Bit(in=in[7], load=load , out=out[7]);
+    Bit(in=in[8], load=load , out=out[8]);
+    Bit(in=in[9], load=load , out=out[9]);
+    Bit(in=in[10], load=load , out=out[10]);
+    Bit(in=in[11], load=load , out=out[11]);
+    Bit(in=in[12], load=load , out=out[12]);
+    Bit(in=in[13], load=load , out=out[13]);
+    Bit(in=in[14], load=load , out=out[14]);
+    Bit(in=in[15], load=load , out=out[15]);
+}
\ No newline at end of file
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