feat: UNIT 2 HDL

2026-01-19 09:10:16 +01:00
parent cad95f4640
commit 7a81edb39e
8 changed files with 186 additions and 0 deletions
--- a/project-2-boolean-arithmetic/hdl/ALU.hdl
+++ b/project-2-boolean-arithmetic/hdl/ALU.hdl
@@ -0,0 +1,90 @@
+// This file is part of www.nand2tetris.org
+// and the book "The Elements of Computing Systems"
+// by Nisan and Schocken, MIT Press.
+// File name: projects/2/ALU.hdl
+/**
+ * ALU (Arithmetic Logic Unit):
+ * Computes out = one of the following functions:
+ *                0, 1, -1,
+ *                x, y, !x, !y, -x, -y,
+ *                x + 1, y + 1, x - 1, y - 1,
+ *                x + y, x - y, y - x,
+ *                x & y, x | y
+ * on the 16-bit inputs x, y,
+ * according to the input bits zx, nx, zy, ny, f, no.
+ * In addition, computes the two output bits:
+ * if (out == 0) zr = 1, else zr = 0
+ * if (out < 0)  ng = 1, else ng = 0
+ */
+// Implementation: Manipulates the x and y inputs
+// and operates on the resulting values, as follows:
+// if (zxxx    // 16-bit constant
+// if (nx == 1) sets x = !x       // bitwise not
+// if (zy == 1) sets y = 0        // 16-bit constant
+// if (ny == 1) sets y = !y       // bitwise not
+// if (f == 1)  sets out = x + y  // integer 2's complement addition
+// if (f == 0)  sets out = x & y  // bitwise and
+// if (no == 1) sets out = !out   // bitwise not
+
+CHIP ALU {
+    IN  
+        x[16], y[16],  // 16-bit inputs        
+        zx, // zero the x input?
+        nx, // negate the x input?
+        zy, // zero the y input?
+        ny, // negate the y input?
+        f,  // compute (out = x + y) or (out = x & y)?
+        no; // negate the out output?
+    OUT 
+        out[16], // 16-bit output
+        zr,      // if (out == 0) equals 1, else 0
+        ng;      // if (out < 0)  equals 1, else 0
+
+    PARTS:
+
+
+    // zx
+    Mux16(a=x, b[0..15]=false , sel=zx, out=zeroedX);
+
+    // nz
+    Not16(in=zeroedX, out=notX);
+    Mux16(a=zeroedX,b=notX,sel=nx, out=processedX);
+
+    //zy
+    Mux16(a=y, b[0..15]=false , sel=zy, out=zeroedY);
+
+    //ny
+    Not16(in=zeroedY, out=notY);
+    Mux16(a=zeroedY,b=notY,sel=ny, out=processedY);
+
+    // f
+    And16(a=processedX , b=processedY , out=andXY);
+    Add16(a=processedX , b=processedY , out=addXY);
+    Mux16(a=andXY, b=addXY,sel=f, out= fOut );
+
+    // no
+    Not16(in=fOut, out=notF);
+    Mux16(a=fOut, b=notF, sel=no, 
+    // variable wire
+    out[0..7]=finalResultp1,
+    out[8..15]=finalResultp2,
+    // out
+    out=out, 
+    out[15]=ng
+    );
+    //zr
+    Or8Way(in=finalResultp1 , out=zr8wayoutp1);
+    Or8Way(in=finalResultp2 , out=zr8wayoutp2);
+
+    Or(a=zr8wayoutp1, b= zr8wayoutp2, out=zrOut);
+
+    Not(in= zrOut, out= zr);
+
+    //ng
+    // output from Mux16 in no
+    
+
+
+    //// Replace this comment with your code.
+    
+}