feat: project 5 start

project-3-sequential-logic/hdl/RAM4K.hdl

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+// This file is part of www.nand2tetris.org
+// and the book "The Elements of Computing Systems"
+// by Nisan and Schocken, MIT Press.
+// File name: projects/3/b/RAM4K.hdl
+/**
+ * Memory of 4K 16-bit registers.
+ * If load is asserted, the value of the register selected by
+ * address is set to in; Otherwise, the value does not change.
+ * The value of the selected register is emitted by out.
+ */
+CHIP RAM4K {
+    IN in[16], load, address[12];
+    OUT out[16];
+
+    PARTS:
+    
+    // Figuring out which RAM512 to write to
+    DMux8Way(
+        in=load,
+        sel=address[9..11],
+        a=load01,
+        b=load02,
+        c=load03,
+        d=load04,
+        e=load05,
+        f=load06,
+        g=load07,
+        h=load08
+    );
+
+    // Writing the correct RAM address inside the register
+    RAM512(in=in, load=load01, address=address[0..8],out=ram512out01);
+    RAM512(in=in, load=load02, address=address[0..8],out=ram512out02);
+    RAM512(in=in, load=load03, address=address[0..8],out=ram512out03);
+    RAM512(in=in, load=load04, address=address[0..8],out=ram512out04);
+    
+    RAM512(in=in, load=load05, address=address[0..8],out=ram512out05);
+    RAM512(in=in, load=load06, address=address[0..8],out=ram512out06);
+    RAM512(in=in, load=load07, address=address[0..8],out=ram512out07);
+    RAM512(in=in, load=load08, address=address[0..8],out=ram512out08);
+
+    // Reading the selected RAM Register
+    Mux8Way16(
+        a=ram512out01,
+        b=ram512out02,
+        c=ram512out03,
+        d=ram512out04,
+        e=ram512out05,
+        f=ram512out06,
+        g=ram512out07,
+        h=ram512out08,
+        sel=address[9..11],
+        out=out
+    );
+}