feat: project 5 start

project-3-sequential-logic/hdl/RAM8.hdl

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+// This file is part of www.nand2tetris.org
+// and the book "The Elements of Computing Systems"
+// by Nisan and Schocken, MIT Press.
+// File name: projects/3/a/RAM8.hdl
+/**
+ * Memory of eight 16-bit registers.
+ * If load is asserted, the value of the register selected by
+ * address is set to in; Otherwise, the value does not change.
+ * The value of the selected register is emitted by out.
+ */
+CHIP RAM8 {
+    IN in[16], load, address[3];
+    OUT out[16];
+
+    PARTS:
+
+    // Only writing if load = 1
+
+    // Selecting which address 16-bit register to write to 
+    DMux8Way(
+        sel=address,
+        in=load,
+        a=load1,
+        b=load2, 
+        c=load3, 
+        d=load4, 
+        e=load5, 
+        f=load6, 
+        g=load7, 
+        h=load8, 
+    );
+    // Writing to the selected register
+    Register(in=in , load=load1 , out= regOut1);
+    Register(in=in , load=load2 , out= regOut2);
+    Register(in=in , load=load3 , out= regOut3);
+    Register(in=in , load=load4 , out= regOut4);
+    Register(in=in , load=load5 , out= regOut5);
+    Register(in=in , load=load6 , out= regOut6);
+    Register(in=in , load=load7 , out= regOut7);
+    Register(in=in , load=load8 , out= regOut8);
+
+    // Outputting the register that is selected
+    Mux8Way16(
+        a=regOut1,
+        b=regOut2,
+        c=regOut3,
+        d=regOut4,
+        e=regOut5,
+        f=regOut6,
+        g=regOut7,
+        h=regOut8,
+        sel=address,
+        out=out
+    );
+}